1. Field of the Invention
The present invention relates to a semiconductor circuit, in particular, to a three-input exclusive NOR circuit widely used arithmetic processing or the like.
2. Description of the Prior Art
FIG. 7 is a diagram showing a truth table of a three-input exclusive NOR circuit. Notations A, B and C shown in the figure are input pins of the circuit and notation Y denotes the output pin thereof. It should be noted that notation X is an intermediate node at which a result of exclusive-OR processing of the three inputs appears. It is worth noting that, in the following description, the notations A, B, C, X and Y are also used to denote signals appearing at the input pins, the intermediate node and the output pin denoted by the notations.
FIG. 8 is a diagram showing a three-input exclusive NOR circuit comprising two two-input exclusive OR circuits and an inverter. Reference numerals 1 and 2 denote the two two-input exclusive OR circuits whereas reference numeral 3 is the inverter. It should be noted that the output of the two-input exclusive OR circuit 2 and the inverter 3 are denoted respectively by the notations X and Y shown in the table of FIG. 7.
FIG. 9 is a diagram illustrating the circuit shown in FIG. 8 in detail. It should be noted that components shown in FIG. 9 identical with those shown in FIG. 8 are denoted by the same notations and reference numerals as those used in FIG. 8 and no duplicate explanation is given. Reference numerals 4 to 7 shown in FIG. 9 each denote an inverter for inverting a signal supplied thereto and reference numerals 8 to 11 are each a CMOS transmission gate. In each of the inverters 4 to 7 and the CMOS transmission gates 8 to 11, an n-channel transistor and a p-channel transistor are employed. Thus, there are a total of 18 transistors employed in the circuit.
The explanation of the detailed operation of the circuit is omitted. The value of the signal B puts either the transmission gate 8 or 9 in a conductive state. By the same token, the value of a signal output by the inverter 5 puts either the transmission gate 10 or 11 in a conductive state.
With respect to the speed of the propagation of signals, a path from the input pin A to the output pin Y through the inverter 4, the transmission gate 8, the inverter 5, the transmission gate 10 (or the transmission gate 11) and the inverter 3 is longest, comprising three inverter stages and two transmission-gate stages.
Next, let attention be paid to power consumption. Power consumed by a CMOS circuit can be classified into two main categories. The first category is power caused by a switching current which flows between a power supply and the ground at the time the output of a CMOS logic gate changes. The second category is power due to a charging/discharging current of a capacitive load. Since a switching current flows through each CMOS logic gate, that is, each of the inverters shown in FIG. 9, one way to reduce the amount of consumed power is to decrease the number of CMOS logic gates employed in the circuit in order to reduce the total amount of the switching currents.
FIG. 10 is a diagram showing a conventional three-input exclusive NOR circuit which is obtained by reducing the number of components employed in the circuit shown in FIG. 9. Reference numerals 12 to 14 shown in FIG. 10 each denote an inverter, reference numerals 15 and 16 are each a p-type transmission gate and reference numerals 17 and 18 are each an n-type transmission gate. Notation W denotes an intermediate node. In the case of the circuit shown in FIG. 10, p-type and n-type transmission gates are employed in place of the CMOS transmission gates. The number of n-type transistors is five and the number of p-type transistors is also five to give a total of 10 transistors. With regard to the speed of the propagation of signals, a path from the input pin A to the output pin Y through the inverter 12, the transmission gate 15, the inverter 13, the transmission gate 16 and the inverter 14 is longest, comprising three inverter stages and two transmission-gate stages.
As for power consumption, because the number of inverters employed in the circuit shown in FIG. 10 is smaller than that of the circuit shown in FIG. 9, the total amount of switching current is also smaller. Since n-type or p-type transmission gates are employed, however, the circuit is affected by a substrate-bias effect. For example, there is observed a phenomenon wherein, even if the source terminal of an n-type transmission gate, which is put in a conductive state by setting the gate terminal at the potential of the power supply, is raised to the potential of the power supply, the drain terminal serving as the output of the transmission gate does not rise to the potential of the power supply. By the same token, even if the source terminal of a p-type transmission gate in a conductive state is pulled down to the potential of the ground, the drain terminal serving as the output of the transmission gate will not go down to the potential of the ground. It should be noted that the potentials of the power supply and the ground are also referred to hereafter as logic values "1" and "0" respectively.
For the reason described above, depending upon the combination of the values of the inputs A, B and C, the potentials of nodes W and X shown in the figure can become an intermediate potential, causing a through current to flow through the inverter 13 or 14. Specifically, there are eight possible combinations of the three inputs A, B and C. There is encountered a problem that, for six combinations other than (A, B, C) =(0, 1, 0) and (0, 1, 1), a DC current inevitably flows.
FIG. 11 is a diagram showing a typical conventional circuit which is obtained by improving the circuit shown in FIG. 10 so that this steady-state through current does not flow. The circuit shown in FIG. 10 is improved by inserting inverters 19 and 20 each with a small driving power. The inverters 19 and 20 are used as feedback circuits for pulling up the nodes W and X to the potential of the power supply and pulling down them to the potential of the ground. It should be noted that components of FIG. 11 identical with those employed in the circuit shown in FIG. 10 are denoted by the same reference numerals as those used in FIG. 10 and no duplicate explanation is thus given. The number of p-type transistors is seven and the number of n-type transistors is also seven to give a total of 14 transistors employed in the circuit shown in FIG. 11. Thus, the number of elements is smaller than that in FIG. 9 but the number of inverters remains five, leaving the circuit unimproved as far as the power consumption is concerned.
The conventional three-input exclusive NOR circuit has the configuration described above, giving rise to a problem that the effect of reduction of power consumption is small even if the number of elements is decreased and the speed is not improved either.